22 research outputs found
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis
Full text link
Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design
No full textFast, accurate static analysis for fixed-point finite-precision effects in DSP designs
No full textIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers275-282DICD
FPGA Implementation of a Maze Routing Accelerator
No full textThis paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-reroute. A 16 X 16 single-layer and 4 X 4 multi-layer router that can handle 2-16 layers have been implemented in a low-end Xilinx XC2S300E FPGA. Larger arrays are currently under construction
Floating-point bit-width optimization for low-power signal processing applications
No full textICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings3III/3208-III/3211IPRO
Lightweight floating-point arithmetic: Case study of inverse discrete cosine transform
No full text10.1155/S1110865702205090Eurasip Journal on Applied Signal Processing20029879-892EJAS
Floating-point error analysis based on affine arithmetic
No full textICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings2561-564IPRO
